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1. Model Introduction

Qwen3.5-397B-A17B is the latest flagship model in the Qwen series developed by Alibaba, representing a significant leap forward with unified vision-language foundation, efficient hybrid architecture, and scalable reinforcement learning. Qwen3.5 features a Gated Delta Networks combined with sparse Mixture-of-Experts architecture (397B total parameters, 17B activated), delivering high-throughput inference with minimal latency. It supports multimodal inputs (text, image, video) and natively handles context lengths of up to 262,144 tokens, extensible to over 1M tokens. Architecture details:
  • Hybrid Attention: Gated Delta Networks (linear, O(n) complexity) combined with full attention every 4th layer — linear layers provide low-cost long-context processing while periodic full attention ensures high associative recall.
  • MoE routing: Top-10 active out of 512 routed experts plus a dedicated shared expert for universal features, keeping 17B parameters active from 397B total.
  • Native multimodal: DeepStack Vision Transformer with Conv3d temporal encoding for image and video understanding without separate visual encoders.
Key Features:
  • Unified Vision-Language Foundation: Early fusion training on multimodal tokens achieves cross-generational parity with Qwen3 and outperforms Qwen3-VL models
  • Efficient Hybrid Architecture: Gated Delta Networks + sparse MoE (397B total / 17B active) for high-throughput inference
  • Hybrid Reasoning: Thinking mode enabled by default with step-by-step reasoning, can be disabled for direct responses
  • Tool Calling: Built-in tool calling support with qwen3_coder parser
  • Multi-Token Prediction (MTP): Speculative decoding support for lower latency
  • 201 Language Support: Expanded multilingual coverage across 201 languages and dialects
Available Models:
ModelBF16 (Full precision)FP8 (8-bit Quantized)FP4 (4-bit Quantized)
Qwen3.5-397B-A17BQwen/Qwen3.5-397B-A17BQwen/Qwen3.5-397B-A17B-FP8NVIDIA NVFP4: nvidia/Qwen3.5-397B-A17B-NVFP4
AMD MXFP4: amd/Qwen3.5-397B-A17B-MXFP4
Qwen3.5-122B-A10BQwen/Qwen3.5-122B-A10BQwen/Qwen3.5-122B-A10B-FP8-
Qwen3.5-35B-A3BQwen/Qwen3.5-35B-A3BQwen/Qwen3.5-35B-A3B-FP8-
Qwen3.5-27BQwen/Qwen3.5-27BQwen/Qwen3.5-27B-FP8-
Qwen3.5-9BQwen/Qwen3.5-9B--
Qwen3.5-4BQwen/Qwen3.5-4B--
Qwen3.5-2BQwen/Qwen3.5-2B--
Qwen3.5-0.8BQwen/Qwen3.5-0.8B--
License: Apache 2.0

2. SGLang Installation

SGLang from the main branch is required for Qwen3.5. You can install from source or use a Docker image:
Command
For the full Docker setup and other installation methods, please refer to the official SGLang installation guide. For SGLang CPU installation, please refer to the CPU version installation guide.

3. Model Deployment

This section provides deployment configurations optimized for different hardware platforms and use cases.

3.1 Basic Configuration

Interactive Command Generator: Use the configuration selector below to automatically generate the appropriate deployment command for your hardware platform and capabilities.

3.2 Configuration Tips

  • Speculative decoding (MTP) can significantly reduce latency for interactive use cases.
  • H100 FP8: Add --enable-symm-mem to enable NCCL symmetric memory for faster collectives and better performance under multi-GPU settings.
  • AMD GPUs (MI300X / MI325X / MI355X): Use SGLANG_USE_AITER=1 and SGLANG_USE_AITER_UNIFIED_ATTN=1 with --attention-backend aiter, which requires --page-size 16 and can also enable --enable-aiter-allreduce-fusion. Additionally set AITER_FLYDSL_FORCE=1 to force the AITER FlyDSL MoE kernels and SGLANG_MAMBA_SSM_DTYPE=bfloat16 to store the Mamba SSM state in bfloat16 (instead of the default float32). For the MXFP4 checkpoint on MI355X, set ROCM_QUICK_REDUCE_QUANTIZATION=INT8 to route multi-GPU collectives through INT8-quantized ROCm quick all-reduce, and drop --enable-aiter-allreduce-fusion (the two are mutually exclusive; quick all-reduce is preferred for this recipe).
  • Watchdog timeout: Increase --watchdog-timeout to 1200 or higher for this large model, as weight loading can take significant time.
  • Mamba Radix Cache: Qwen3.5’s hybrid Gated Delta Networks architecture supports two mamba scheduling strategies via --mamba-radix-cache-strategy:
    • V1 (no_buffer): Default. No overlap scheduler, lower memory usage. Required for AMD MI GPUs.
    • V2 (extra_buffer): Enables overlap scheduling and branching point caching with --mamba-radix-cache-strategy extra_buffer --page-size 64. Requires FLA kernel backend (NVIDIA GPUs only). Trades higher mamba state memory for better throughput. Strictly superior in non-KV-cache-bound scenarios; in KV-cache-bound cases, weigh the overlap scheduling benefit against reduced max concurrency. --page-size must satisfy FLA_CHUNK_SIZE % page_size == 0 or page_size % FLA_CHUNK_SIZE == 0 (FLA_CHUNK_SIZE is currently 64).
  • The --mem-fraction-static flag is recommended for optimal memory utilization, adjust it based on your hardware and workload.
  • Context length defaults to 262,144 tokens. If you encounter OOM errors, consider reducing it, but maintain at least 128K to preserve thinking capabilities.
  • To speed up weight loading for this large model, add --model-loader-extra-config='{"enable_multithread_load": "true","num_threads": 64}' to the launch command.
  • CUDA IPC Transport: Add SGLANG_USE_CUDA_IPC_TRANSPORT=1 as an environment variable to use CUDA IPC for transferring multimodal features, significantly improving TTFT (Time To First Token). Note: this consumes additional memory proportional to image size, so you may need to lower --mem-fraction-static or --max-running-requests.
  • Multimodal Attention Backend: Use --mm-attention-backend fa3 on H100/H200 for better vision performance, or --mm-attention-backend fa4 on B200/B300.
  • B200 (FP8): Add --enable-flashinfer-allreduce-fusion for optimized throughput on Blackwell.
  • For processing large images or videos, you may need to lower --mem-fraction-static to leave room for image feature tensors.
  • Hardware requirements:
    • BF16: ~397B parameters require ~800GB of GPU memory for weights.
      • H100 (80GB) requires tp=16 (2 nodes) since each rank needs ~100GB at tp=8.
      • H200 (141GB) runs with tp=8.
      • B200 (183GB) runs with tp=8.
      • B300 (275GB) runs with tp=4.
      • MI300X (192GB) runs with tp=8.
      • MI325X (256GB) runs with tp=4.
      • MI355X (288GB) runs with tp=4.
    • FP8: The FP8 quantized model requires ~400GB for weights, cutting memory in half.
      • H100 (80GB) runs with tp=8.
      • H200 (141GB) runs with tp=4.
      • B200 (183GB) runs with tp=4.
      • B300 (275GB) runs with tp=2.
      • MI300X (192GB) runs with tp=4.
      • MI325X (256GB) runs with tp=2.
      • MI355X (288GB) runs with tp=2.
    • FP4: The FP4 quantized model requires ~250GB for weights, cutting memory by almost 4x. NVFP4 (nvidia/Qwen3.5-397B-A17B-NVFP4) requires B200/B300 (Blackwell architecture); AMD provides an MXFP4 checkpoint (amd/Qwen3.5-397B-A17B-MXFP4) for MI355X.
      • B200 (183GB) runs with tp=4. (NVFP4)
      • B300 (275GB) runs with tp=2. (NVFP4)
      • MI355X (288GB) runs with tp=2 (use tp=4 for low concurrency). (MXFP4)
HardwareMemoryBF16 TPFP8 TPFP4 TP
H10080GB168N/A
H200141GB84N/A
B200183GB844
B300275GB422
MI300X192GB84N/A
MI325X256GB42N/A
MI355X288GB422 / 4 (MXFP4)
FP8 KV Cache: --kv-cache-dtype fp8_e4m3 quantizes the KV cache to FP8 at runtime. Since these FP8 model checkpoints do not include pre-calibrated KV cache scaling factors, SGLang defaults to a scale of 1.0, which may cause noticeable accuracy degradation on reasoning-heavy tasks. It is not included in the generated commands above; add it manually only if memory constraints require the trade-off.
  • Xeon CPU service configuration: Please refer to the Notes part in the serving engine launching section in the SGLang CPU server document to better understand how to configure the arguments, especially for TP (tensor parallel) and NUMA binding settings.

4. Model Invocation

NVIDIA: Deploy Qwen3.5-397B-A17B with the following command (H200, all features enabled):
Command
AMD: Deploy Qwen3.5-397B-A17B with the following command (MI300X/MI325X/MI355X):
Command
Note: To enable MTP (speculative decoding), append --speculative-algorithm EAGLE --speculative-num-steps 3 --speculative-eagle-topk 1 --speculative-num-draft-tokens 4.

4.1 Basic Usage

For basic API usage and request examples, please refer to:

4.2 Vision Input

Qwen3.5 supports image and video inputs as a unified vision-language model. Here is an example with an image:
Example
Output Example:
Output

4.3 Advanced Usage

4.3.1 Reasoning Parser

Qwen3.5 supports Thinking mode by default. Enable the reasoning parser during deployment to separate the thinking and content sections. The thinking process is returned via reasoning_content in the streaming response. To disable thinking and use Instruct mode, pass chat_template_kwargs at request time:
  • Thinking mode (default): The model performs step-by-step reasoning before answering. No extra parameters needed.
  • Instruct mode ({"enable_thinking": false}): The model responds directly without a thinking process.
Example 1: Thinking Mode (Default) Thinking mode is enabled by default. The model will reason step-by-step before answering, and the thinking process is returned via reasoning_content:
Example
Output Example:
Output
Example 2: Instruct Mode (Thinking Off) To disable thinking and get a direct response, pass {"enable_thinking": false} via chat_template_kwargs:
Example
Output Example:
Output

4.3.2 Tool Calling

Qwen3.5 supports tool calling capabilities. Enable the tool call parser during deployment. Thinking mode is on by default; to disable it for tool calling requests, pass extra_body={"chat_template_kwargs": {"enable_thinking": False}}. Python Example (with Thinking Process):
Example
Output Example:
Output

5. Benchmark

5.1 Accuracy Benchmark

5.1.1 GSM8K Benchmark

  • Benchmark Command
Command
  • Test Result
Output

5.1.2 GSM8K with lm-eval (5-shot)

Evaluate using the industry-standard lm-eval harness for reproducible accuracy reporting:
Command

5.1.3 MMMU Benchmark

  • Benchmark Command
Command
  • Test Result
Output

5.2 Speed Benchmark

Test Environment:
  • Hardware: H200 (8x)
  • Model: Qwen3.5-397B-A17B
  • Tensor Parallelism: 8
  • SGLang Version: main branch
Server Launch Command:
Command

5.2.1 Latency Benchmark

Command
Output

5.2.2 Throughput Benchmark

Command
Output

5.3 Vision Speed Benchmark

We use SGLang’s built-in benchmarking tool to conduct performance evaluation with random images. Each request has 128 input tokens, two 720p images, and 1024 output tokens.

5.3.1 Latency Benchmark

Command
Output

5.3.2 Throughput Benchmark

Command
Output