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1. Quick start

Install the diffusion dependencies on Linux with NVIDIA CUDA, then install this integration from its source checkout:
Installation
Use the official circlestone-labs/Anima-Base-v1.0-Diffusers checkpoint. SGLang reads its modular_model_index.json directly; no checkpoint conversion or newer Diffusers runtime is required. Start with Resident + Compiled for repeated generation on RTX 5090, DGX Spark, or H200. Select Eager for shorter startup or frequent shape changes. Spark’s 128 GB is unified memory shared with the CPU, not dedicated VRAM. See the measurements and tradeoffs below.

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2. Model capabilities

Anima is CircleStone Labs and Comfy Org’s text-to-image model for anime and illustration. It combines a Cosmos Predict2 transformer with Qwen3 text encoding, a learned T5-token conditioner, and a Qwen-Image VAE. Prompts can combine tags with natural-language descriptions. This integration targets Base v1.0 text-to-image. It does not claim support for the separate Aesthetic or Turbo checkpoints, single-file ComfyUI weights, or image editing. The checkpoint uses the CircleStone Labs Non-Commercial License; review the official license before deployment.

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3. Sampling

Defaults are 1024 x 1024, 30 steps, guidance scale 4, and an empty negative prompt. Width and height should be divisible by 16. max_sequence_length defaults to 512 and accepts 1 through 4096. The text conditioner pads short sequences to 512 tokens; these padding positions remain part of the transformer’s cross-attention, matching the official implementation. For offline generation:
Generate
Use the same seed, generator device, dimensions, scheduler settings, and precision when comparing runtimes. Latents and scheduler updates remain FP32; the transformer, text components, and VAE default to BF16. Different attention kernels can produce small floating-point differences that accumulate during denoising.

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4. Runtime features

The pipeline reuses SGLang’s native Qwen3 encoder, Qwen-Image VAE, component loaders, denoising loop, and residency management. Anima’s transformer and text conditioner are native modules, not wrappers around Diffusers models. For multi-GPU execution, choose TP to shard transformer weights or Ulysses/Ring to shard image tokens. The transformer has 16 heads, so tp_size * ulysses_degree must divide 16. CFG parallelism additionally splits conditional and unconditional denoising and requires guidance greater than 1. The total GPU count must match the selected parallel topology. CPU and layerwise offload trade memory for transfers. The additional text_conditioner component accepts the same residency controls as other native components. Cache-DiT and quantized attention are approximate optimizations; assess image quality for your prompts before enabling them. See performance optimization for the shared controls. H200 functional checks cover TP, Ulysses, Ring, CFG parallelism, encoder folding, parallel tiled VAE decode, layerwise offload, FlashAttention, Torch SDPA, SageAttention, Cache-DiT, and breakable CUDA graphs. These checks are not a quality guarantee for approximate optimizations. Combined TP and SP, multi-node execution, non-NVIDIA devices, and third-party LoRAs remain unverified. Breakable CUDA graphs reuse the conditioner’s actual sequence length, without additional text-bucket padding. Requests with uncaptured shapes fall back to eager execution. Standard short prompts use the same 512-token conditioning shape.

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5. Measured tuning

For repeated requests, compilation was faster than eager execution on all three tested platforms. The picker keeps eager available because initial compilation and recompilation for new shapes can take minutes and use additional CPU memory. No CPU offload, quantized attention, or Cache-DiT is enabled in the recommended recipes. The following are warm, sequential HTTP request medians: 1024 x 1024, 30 steps, CFG 4, one image, CPU generator, and PNG/base64 output. Startup is excluded. Measurements used five timed requests after warmup, PyTorch 2.13.0+cu130, and the native Anima implementation at 214c9a48bb1 (Spark used 7f3f903f039, with identical runtime code). Results are workload-specific, not throughput-at-saturation measurements. The original eager baseline uses Torch SDPA on 5090/Spark and FlashAttention on H200, with VAE tiling enabled. Peak allocated memory excludes the CUDA context, reserved pool, and compilation CPU memory; it is not total device usage. On two NVLink-connected H200s, Auto selects CFG parallelism instead of TP: the compiled, untiled recipe measured 1.28 s. Untiled decoding trades about 4-5 GiB more allocated memory for lower latency and is verified at 1024 x 1024, one output. The tiled recipes additionally passed repeated 512 x 512 and 1536 x 1536 requests, plus two outputs at 1024 x 1024. Use Tiled for that verified scope. At 512 x 512, two-GPU CFG eager was faster than compiled; more GPUs or compilation are not universally better. The recommended recipes change floating-point kernels and, on H200, VAE tiling. They are not pixel-identical to eager: across three fixed prompt/seed pairs, the single-GPU recipes above measured PSNR 21.95-35.44 dB and SSIM 0.851-0.969 against their same-device eager outputs. These measure output differences, not perceptual quality guarantees. Use eager with the same backend and tiling settings when reproducing an eager reference. Breakable CUDA graphs were near parity at 1024 x 1024 while consuming about 1.2 GiB more allocated GPU memory for a single captured shape. They are not the default. Cache-DiT can accelerate further, but changes the denoising computation; validate it separately against your quality requirements.